FPGA 连续实战 · 02 板卡配置与约束编写

# Reference: Digilent Basys-3-Master.xdc (rev B reference).
# ONLY use after matching the actual board schematic and bank voltage.
set_property PACKAGE_PIN W5 [get_ports clk]
set_property PACKAGE_PIN U18 [get_ports btnC]
set_property PACKAGE_PIN U16 [get_ports {led[0]}]
set_property PACKAGE_PIN E19 [get_ports {led[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {clk btnC led[*]}]
create_clock -name sys_clk -period 10.000 [get_ports clk]

# Asynchronous human button: exempt ONLY the first synchronizer D endpoint.
set first_stage [get_pins -hier -filter {NAME =~ *u_reset/btn_meta_reg/D}]
if {[llength $first_stage] != 1} {error "FPGA_XDC: first synchronizer endpoint is missing or ambiguous"}
set_false_path -from [get_ports btnC] -to $first_stage
# Human-viewed status LEDs are not sampled by an external synchronous receiver.
set_false_path -to [get_ports {led[0] led[1]}]
# No broad exception between synchronizer stages or on internal FIFO paths.

python3 flow.py prepare baseline --ila
# FPGA_PREPARED name=baseline BUILD_ID=<实际摘要> ila=True fault=False
cat build/baseline/manifest.json
cat build/baseline/config.tcl
# set build_id <实际八位十六进制值>
# set enable_ila 1
# set inject_error 0