Palladium 事务级实战 · 03 实现硬件侧 transactor

// Original synthesizable transaction engine. One command in flight, max 32 bytes.
module batch_engine(input wire clk,rst,
 input wire req_valid,output wire req_ready,input wire [15:0] req_id,
 input wire [5:0] req_len,input wire [255:0] req_data,
 output wire rsp_valid,input wire rsp_ready,output reg [15:0] rsp_id,
 output reg [5:0] rsp_len,output reg [1:0] rsp_status,
 output reg [255:0] rsp_data,output reg [31:0] rsp_cycles);
 localparam IDLE=0,ACTIVE=1,RESPONSE=2;
 reg [1:0] state=IDLE;
 reg [255:0] data;
 reg [5:0] length,pushed,popped,captured;
 reg pending_read;
 wire full,empty;wire [7:0] dout;wire [2:0] count;
 wire wr_en=state==ACTIVE && pushed<length;
 // A fixed, repeatable drain pause exercises FIFO full/backpressure.
 wire rd_en=state==ACTIVE && popped<length && rsp_cycles[2:0]>=3;
 wire [7:0] din=data[8*pushed+:8];
 course_fifo dut_i(clk,rst,wr_en,rd_en,din,dout,full,empty,count);
 assign req_ready=state==IDLE && !rst;
`ifdef DROP_RESPONSE
 assign rsp_valid=1'b0;
`else
 assign rsp_valid=state==RESPONSE && !rst;
`endif
 always @(posedge clk) begin
  if(rst)begin
   state<=IDLE;data<=0;length<=0;pushed<=0;popped<=0;captured<=0;
   pending_read<=0;rsp_id<=0;rsp_len<=0;rsp_status<=0;rsp_data<=0;rsp_cycles<=0;
  end else case(state)
   IDLE:if(req_valid)begin
    data<=req_data;length<=req_len;pushed<=0;popped<=0;captured<=0;pending_read<=0;
`ifdef BAD_TAG
    rsp_id<=req_id^16'h1;
`else
    rsp_id<=req_id;
`endif
    rsp_len<=req_len;rsp_data<=0;rsp_cycles<=0;
    if(req_len==0 || req_len>32)begin rsp_status<=2;state<=RESPONSE;end
    else begin rsp_status<=0;state<=ACTIVE;end
   end
   ACTIVE:begin
    rsp_cycles<=rsp_cycles+1;
    if(wr_en&&!full)pushed<=pushed+1'b1;
    pending_read<=rd_en&&!empty;
    if(rd_en&&!empty)popped<=popped+1'b1;
    // FIFO dout updates on the read edge; consume it on the following edge.
    if(pending_read)begin
     rsp_data[8*captured+:8]<=dout;captured<=captured+1'b1;
     if(captured+1==length)state<=RESPONSE;
    end
   end
   RESPONSE:if(rsp_ready)state<=IDLE;
   default:state<=IDLE;
  endcase
 end
endmodule

`timescale 1ns/1ps
// Palladium reference flow maps this generator using +iscDelay+clk_gen.
// Do not treat a free-running #delay as ordinary synthesizable RTL.
module clk_gen(output reg clk=0);
 always #5 clk=~clk;
endmodule