FPGA 流式实战 · 03 流控反压与复位恢复

module stream_sink #(parameter N=4096,MODE=0)(input wire clk,rst,
 input wire [31:0] data,input wire [3:0] keep,input wire last,valid,
 output wire ready,output reg [31:0] received,bytes,packets,cycles,
 output reg done,fail);
 wire expected_last=received[2:0]==7;
 wire [3:0] expected_keep=expected_last?4'h3:4'hf;
 wire [31:0] expected_data=32'h60000000+received*17+3;
 assign ready=!rst && !done && (MODE==0 || (MODE==1?cycles[2:0]<5:cycles>=80));
 always @(posedge clk or posedge rst)begin
  if(rst)begin received<=0;bytes<=0;packets<=0;cycles<=0;done<=0;fail<=0;end
  else if(!done)begin
   cycles<=cycles+1'b1;
   if(valid && ready)begin
    if(data!=expected_data || keep!=expected_keep || last!=expected_last)fail<=1;
    received<=received+1'b1;bytes<=bytes+{31'b0,keep[0]}+{31'b0,keep[1]}+{31'b0,keep[2]}+{31'b0,keep[3]};
    if(last)packets<=packets+1'b1;
    if(received==N-1)done<=1;
   end
  end
 end
endmodule

python3 flow.py sim --stall-fault
# OUTPUT_UNSTABLE: backpressure overwrote payload
# STREAM_NEGATIVE_PASS
python3 flow.py sim --fault
# STREAM_MISMATCH beat=0，首拍 0x60000003 被改成 0x60000002
# STREAM_NEGATIVE_PASS
python3 flow.py bist --fault
# 软件模型两轮 led=11