FPGA 进阶实战 · 02 AXI4-Lite 寄存器与反压

`timescale 1ns/1ps
module axi_mailbox #(parameter INJECT_ERROR=0)(
 input wire aclk,arst,dclk,drst,
 input wire [7:0] awaddr,input wire [2:0] awprot,input wire awvalid,output wire awready,
 input wire [31:0] wdata,input wire [3:0] wstrb,input wire wvalid,output wire wready,
 output reg [1:0] bresp,output reg bvalid,input wire bready,
 input wire [7:0] araddr,input wire [2:0] arprot,input wire arvalid,output wire arready,
 output reg [31:0] rdata,output reg [1:0] rresp,output reg rvalid,input wire rready,
 output wire [79:0] debug_s,debug_d);
 reg aw_pending,w_pending;reg [7:0] addr_q;reg [31:0] data_q;reg [3:0] strb_q;
 reg [31:0] data_reg,result_reg;reg busy,done,start;
 wire mb_ready,mb_valid;wire [31:0] mb_result;
 // PROT is accepted but not used: no security boundary in this teaching peripheral.
 assign awready=!arst && !aw_pending && !bvalid;
 assign wready=!arst && !w_pending && !bvalid;
 assign arready=!arst && !rvalid;
 cdc_mailbox #(.INJECT_ERROR(INJECT_ERROR)) u_cdc(aclk,arst,dclk,drst,start,data_reg,mb_ready,mb_valid,mb_result,debug_s,debug_d);
 integer k;
 always @(posedge aclk or posedge arst) begin
  if(arst) begin
   aw_pending<=0;w_pending<=0;addr_q<=0;data_q<=0;strb_q<=0;
   bresp<=0;bvalid<=0;rresp<=0;rvalid<=0;rdata<=0;
   data_reg<=0;result_reg<=0;busy<=0;done<=0;start<=0;
  end else begin
   start<=0;
   if(bvalid && bready)bvalid<=0;
   if(rvalid && rready)rvalid<=0;
`ifdef BUG_AW_W
   // Intentional fault: wrongly requires simultaneous AWVALID and WVALID.
   if(awvalid && awready && wvalid)begin addr_q<=awaddr;aw_pending<=1;end
   if(wvalid && wready && awvalid)begin data_q<=wdata;strb_q<=wstrb;w_pending<=1;end
`else
   if(awvalid && awready)begin addr_q<=awaddr;aw_pending<=1;end
   if(wvalid && wready)begin data_q<=wdata;strb_q<=wstrb;w_pending<=1;end
`endif
   if(mb_valid)begin result_reg<=mb_result;busy<=0;done<=1;end
   if(aw_pending && w_pending && !bvalid)begin
    aw_pending<=0;w_pending<=0;bvalid<=1;bresp<=0;
    case(addr_q)
     8'h00:for(k=0;k<4;k=k+1)if(strb_q[k])data_reg[k*8+:8]<=data_q[k*8+:8];
     8'h04:if(strb_q[0] && data_q[0])begin
      if(busy || !mb_ready)bresp<=2; // SLVERR, no command accepted
      else begin busy<=1;done<=0;start<=1;end
     end
     default:bresp<=2;
    endcase
   end
   if(arvalid && arready)begin
    rvalid<=1;rresp<=0;
    case(araddr)
     8'h00:rdata<=data_reg;
     8'h08:rdata<={30'b0,done,busy};
     8'h0c:rdata<=result_reg;
     default:begin rdata<=0;rresp<=2;end
    endcase
   end
  end
 end
endmodule

python3 flow.py sim
# 测试中的字节写：
# DATA <- 0x11223344, WSTRB=0xf
# DATA <- 0xaabbccdd, WSTRB=0x5
# 读回应为 0x11bb33dd；WSTRB=0 不修改
python3 flow.py sim --axi-fault
# 预期：AXI_TIMEOUT，随后 ADV_NEGATIVE_PASS