FPGA 进阶实战 · 03 多位跨域握手与复位契约

`timescale 1ns/1ps
// Bundled-data request/acknowledge. Both domains MUST share reset assertion.
(* KEEP_HIERARCHY="yes" *)
module cdc_mailbox #(parameter INJECT_ERROR=0)(
 input wire s_clk,s_rst,d_clk,d_rst,start,input wire [31:0] payload,
 output wire ready,output reg result_valid,output reg [31:0] result,
 output wire [79:0] debug_s,debug_d);
 reg [31:0] held_data;
 reg req,ack,seen_ack;
 (* ASYNC_REG="TRUE" *) reg ack_meta,ack_sync;
 (* ASYNC_REG="TRUE" *) reg req_meta,req_sync;
 reg [31:0] return_data;
 reg [2:0] state;
 wire [31:0] fifo_out;wire full,empty;wire [2:0] count;
 wire [31:0] transformed=held_data ^ 32'h5a5aa5a5 ^ (INJECT_ERROR?32'h1:32'h0);
 course_fifo u_fifo(d_clk,d_rst,state==1,state==2,transformed,fifo_out,full,empty,count);
 assign ready=(req==ack_sync);
 always @(posedge s_clk or posedge s_rst) begin
  if(s_rst) begin held_data<=0;req<=0;seen_ack<=0;ack_meta<=0;ack_sync<=0;result_valid<=0;result<=0;end
  else begin
   ack_meta<=ack;ack_sync<=ack_meta;result_valid<=0;
   if(start && ready) begin held_data<=payload;req<=~req;end
   if(ack_sync!=seen_ack) begin result<=return_data;result_valid<=1;seen_ack<=ack_sync;end
  end
 end
 always @(posedge d_clk or posedge d_rst) begin
  if(d_rst) begin req_meta<=0;req_sync<=0;ack<=0;return_data<=0;state<=0;end
  else begin
   req_meta<=req;req_sync<=req_meta;
   case(state)
    0:if(req_sync!=ack)state<=1;
    1:if(!full)state<=2;
    2:if(!empty)state<=3;
    3:begin return_data<=fifo_out;ack<=req_sync;state<=0;end
   endcase
  end
 end
 assign debug_s={8'b0,held_data,result,req,ack_sync,ready,result_valid,start,s_rst,2'b0};
 assign debug_d={7'b0,fifo_out,return_data,req_sync,ack,state,count,d_rst};
endmodule

(* KEEP_HIERARCHY="yes" *)
module reset_domain(input wire clk,async_reset,output wire rst);
 (* ASYNC_REG="TRUE" *)reg [2:0] pipe=3'b111;
 always @(posedge clk or posedge async_reset)
  if(async_reset)pipe<=3'b111;else pipe<={pipe[1:0],1'b0};
 assign rst=pipe[2];
endmodule