FPGA 流式实战 · 05 Gray 总线与存储路径时序约束

# Basys 3 only. Match the physical board revision and bank voltage before programming.
set_property PACKAGE_PIN W5 [get_ports clk]
set_property PACKAGE_PIN U18 [get_ports btnC]
set_property PACKAGE_PIN U16 [get_ports {led[0]}]
set_property PACKAGE_PIN E19 [get_ports {led[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {clk btnC led[*]}]
create_clock -name sys_clk -period 10.000 [get_ports clk]
# Clocking Wizard generates related 100 MHz write and 50 MHz read clocks.
set_false_path -to [get_ports {led[*]}]
set rp [get_pins -hier -filter {NAME =~ *u_reset_*/pipe_reg*/PRE}]
if {[llength $rp]!=6} {error "STREAM_XDC: expected six reset synchronizer PRE pins"}
set_false_path -to $rp
# Gray pointer bus: constrain arrival delay and skew. No false-path override here.
foreach {src dst limit} {wgray wgray_meta 10.000 rgray rgray_meta 20.000} {
 set from_cells [get_cells -hier -filter "NAME =~ *u_fifo/${src}_reg*"]
 set to_cells [get_cells -hier -filter "NAME =~ *u_fifo/${dst}_reg*"]
 if {[llength $from_cells]!=5 || [llength $to_cells]!=5} {error "STREAM_XDC: inspect all five bits of $src -> $dst"}
 set_max_delay $limit -datapath_only -from $from_cells -to $to_cells
 set_bus_skew $limit -from $from_cells -to $to_cells
}
# Memory payload is protected by pointer ownership and delayed publication, not bit synchronizers.
# Keep RAM-to-output timing analyzed with related clocks; inspect RAM primitive mapping and read paths.
# Never blanket-cut all write/read clocks. Independent board clocks require a new payload timing review.

python3 flow.py prepare baseline --ila
python3 flow.py vivado baseline synth
python3 flow.py vivado baseline impl
# 检查 reports/bus_skew.rpt、cdc.rpt、exceptions.rpt
# clocks.rpt、clock_interaction.rpt、routed_timing.rpt、DRC
cp build/baseline/review.template.txt build/baseline/review.txt
# 填写真实 Gray 位级路径、RAM 读路径和 STA 审查证据
python3 flow.py vivado baseline bit