FPGA 流式实战 · 02 异步 FIFO、Gray 指针与输出槽

`timescale 1ns/1ps
// 16 RAM entries + 1 registered read-side output slot. Common reset assertion required.
(* KEEP_HIERARCHY="yes" *)
module axis_async_fifo #(parameter INJECT_ERROR=0)(
 input wire s_clk,s_rst,input wire [31:0] s_data,input wire [3:0] s_keep,
 input wire s_last,s_valid,output wire s_ready,
 input wire m_clk,m_rst,output wire [31:0] m_data,output wire [3:0] m_keep,
 output wire m_last,output reg m_valid,input wire m_ready,
 output wire [63:0] debug_w,debug_r);
 (* ram_style="distributed" *) reg [36:0] mem[0:15];
 reg [4:0] wbin,wgray,rbin,rgray;
 (* ASYNC_REG="TRUE" *)reg [4:0] rgray_meta,rgray_sync,wgray_meta,wgray_sync;
 reg full,empty;
 reg [36:0] out_word;
 wire push=s_valid && s_ready;
`ifdef BUG_BACKPRESSURE
 wire fetch=!empty; // Deliberate overwrite of a stalled output slot.
`else
 wire fetch=!empty && (!m_valid || m_ready);
`endif
 wire [4:0] wnext=wbin+push,rnext=rbin+fetch;
 wire [4:0] wgray_next=(wnext>>1)^wnext,rgray_next=(rnext>>1)^rnext;
 assign s_ready=!s_rst && !full;
 assign {m_last,m_keep,m_data}=out_word;
 always @(posedge s_clk)if(push)mem[wbin[3:0]]<={s_last,s_keep,s_data};
 always @(posedge s_clk or posedge s_rst)begin
  if(s_rst)begin wbin<=0;wgray<=0;rgray_meta<=0;rgray_sync<=0;full<=0;end
  else begin
   rgray_meta<=rgray;rgray_sync<=rgray_meta;
   wbin<=wnext;wgray<=wgray_next;
   full<=(wgray_next=={~rgray_sync[4:3],rgray_sync[2:0]});
  end
 end
 always @(posedge m_clk or posedge m_rst)begin
  if(m_rst)begin rbin<=0;rgray<=0;wgray_meta<=0;wgray_sync<=0;empty<=1;m_valid<=0;out_word<=0;end
  else begin
   wgray_meta<=wgray;wgray_sync<=wgray_meta;
   rbin<=rnext;rgray<=rgray_next;empty<=(rgray_next==wgray_sync);
   if(fetch)begin
    out_word<=mem[rbin[3:0]] ^ (INJECT_ERROR?37'h1:37'h0);m_valid<=1;
   end else if(m_ready)m_valid<=0;
  end
 end
 assign debug_w={40'b0,wbin,wgray,rgray_sync,full,s_valid,s_ready,s_last,s_keep,s_rst};
 assign debug_r={2'b0,out_word,rbin,rgray,wgray_sync,empty,m_valid,m_ready,fetch,m_rst,5'b0};
endmodule

python3 flow.py sim
# 长暂停场景：MODE=2，前 80 个读周期不接收
# 内部容量检查：sent == 17
# 失败标识：CAPACITY_EXPECTED_17 / FULL_NOT_EXERCISED
# 排空后继续观察 20 个读周期，不能出现 EXTRA_BEAT